Rishikesh Singh

Embedded systems · SoC architecture · Power & performance

Engineering efficient, dependable systems from silicon up.

I’m an embedded systems engineer with 5+ years of experience working across ARM-based multicore SoCs. My work connects architecture, measurement, and low-level software to make complex automotive platforms faster, more efficient, and easier to bring to life.

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01 / Selected work

Depth across the system

Selected engineering contributions spanning measurement, performance, architecture, and first-silicon validation.

Power measurement · AI workloads

Turning rail-level measurements into performance-per-watt insight

Built a bare-metal, real-time utility to measure voltage, current, and total power across SoC rails. Applied it to AI inference workloads to correlate DRAM, core, and accelerator consumption with throughput.

  • IPS/W
  • Power budgeting
  • Competitive analysis

OutcomeWorkload-level visibility for architecture and efficiency decisions.

Memory systems · Characterization

Quantifying the memory hierarchy, not guessing at it

Developed a C-based framework to characterize TCM, cache, SRAM, DRAM, and NVM behavior. Profiled CPU, memory, cache, and NoC subsystems across runtime, standby, and low-power modes to expose system bottlenecks.

  • CoreMark-Pro
  • LMbench
  • NoC analysis

OutcomeEvidence-led recommendations and a measured performance gain of more than 15%.

Architecture · Power management

Designing power behavior as a system-level concern

Worked with SoC architecture and design teams on power domains, reset sequencing, operating modes, and next-generation processor requirements. Developed DVFS algorithms and evaluated voltage, frequency, and performance trade-offs at system level.

  • DVFS
  • DMIPS/W
  • Power states

OutcomeClearer trade-offs across performance, runtime power, and standby power.

First silicon · Platform enablement

Bringing up complex automotive SoCs across hardware and software

Led bring-up and subsystem characterization for ARM-based 5nm multicore automotive SoCs. Developed low-level C validation and diagnostic software for PCIe, eMMC, SD, and Flash, and enabled Linux boot across multiple storage paths.

  • S32N55 / S32N79
  • HW/SW debug
  • Boot flow

OutcomeFaster subsystem validation and confident platform initialization.

02 / Experience

Progression through ownership

From hands-on validation to architecture-level decisions and technical leadership.

Apr 2025 — Present

Lead

Lead Systems & Applications Engineer, G2L

NXP Semiconductors · Noida, India

  • Owns power and performance characterization spanning rail-level measurement, AI workloads, memory hierarchy, and NoC behavior.
  • Develops DVFS approaches and evaluates system-level performance-per-watt trade-offs.
  • Contributes to power and reset architecture for next-generation automotive processors.
  • Represents NXP through Campus Connect sessions on SoC architecture and embedded systems.

Apr 2023 — Apr 2025

Senior

Senior Systems & Applications Engineer, G2

NXP Semiconductors · Noida, India

  • Supported customer power architectures using VR5510 and PF53 PMICs, optimizing power trees, runtime behavior, and standby power.
  • Led first-silicon bring-up, schematic reviews, boot-flow analysis, and subsystem characterization for multicore automotive SoCs.
  • Created customer-facing power calculators, boot-process material, hardware design guides, and engineering bulletins.
  • Enabled and debugged Linux boot from eMMC, UFS, and SD through bootloader and platform configuration.

Jul 2021 — Apr 2023

Engineer

Systems & Applications Engineer, G1

NXP Semiconductors · Noida, India

  • Optimized single- and multicore benchmarks across S32G and S32N processors, improving memory performance by more than 15%.
  • Resolved customer hardware and software issues while maintaining low resolution time and near-zero escalations.
  • Owned errata reports for the S32G2 and S32G3 processor families.
  • Presented new NXP technologies and products in technical customer forums.

03 / Expertise

An engineer’s toolkit

Capabilities built through architecture work, first-silicon programs, and platform delivery.

01

Architecture & efficiency

SoC architecture, performance analysis, power architecture, PVT characterization, DVFS, power domains and states, runtime and standby power.

02

Performance engineering

Benchmarking and modelling, workload analysis, memory hierarchy, system bottleneck analysis, AI inference per second per watt.

03

Boot & low-level systems

Boot architecture, secure boot, BootROM and bootloaders, ARM Cortex-M/R/A, Embedded C/C++, Python, Bash, and Linux bring-up.

04

Silicon & platform debug

Board and silicon bring-up, schematic review, HW/SW debugging, LTB/TPIU tracing, S32 Debug Probe, validation, RCA, and AUTOSAR tooling.

04 / Education

Foundation

2017 — 2021

Bachelor of Technology

Electrical & Electronics Engineering · GPA 7.49/10

National Institute of Technology, Warangal

Thesis: Effect of Zero Vector Placement in an Inverter Fed Induction Motor Drive

05 / Contact

Let’s talk systems.

Email officialrishikesh@gmail.com LinkedIn linkedin.com/in/21rishikesh Phone +91 95198 33289